IDT54FCT16270ATPA中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION:

The FCT162701T/AT is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be used as a read/write buffer between a CPU and memory or to interface a high-speed bus and a slow peripheral. The Ato-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. A HIGH on LE, allows data to flow transparently from B-to-A. A LOW on LE allows the data to be latched on the falling edge of LE.

The FCT162701T/AT has a balanced output drive with series termination. This provides low ground bounce, minimal undershoot and controlled output edge rates.

FEATURES:

? 0.5 MICRON CMOS Technology

? Typical tSK(o) (Output Skew) < 250ps

? Low input and output leakage ≤1μA (max.)

? ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

? Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack

? Extended commercial range of -40°C to +85°C

? Balanced Output Drivers: ±24mA (commercial),

±16mA (military)

? Reduced system switching noise

? Typical VOLP (Output Ground Bounce) < 0.6V at

VCC = 5V, TA = 25°C

? Ideal for new generation x86 write-back cache solutions

? Suitable for modular x86 architectures

? Four deep write FIFO

? Latch in read path

? Synchronous FIFO reset