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IDT54FCT388915T100PY中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

IDT54FCT388915T100PY
廠商型號(hào)

IDT54FCT388915T100PY

功能描述

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

文件大小

145.69 Kbytes

頁(yè)面數(shù)量

11 頁(yè)

生產(chǎn)廠商 Integrated Device Technology, Inc.
企業(yè)簡(jiǎn)稱(chēng)

IDT

中文名稱(chēng)

Integrated Device Technology, Inc.官網(wǎng)

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數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-1-4 16:48:00

IDT54FCT388915T100PY規(guī)格書(shū)詳情

DESCRIPTION:

The IDT54/74FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock.

FEATURES:

? 0.5 MICRON CMOS Technology

? Input frequency range: 10MHz – f2Q Max. spec

(FREQ_SEL = HIGH)

? Max. output frequency: 150MHz

? Pin and function compatible with FCT88915T, MC88915T

? 5 non-inverting outputs, one inverting output, one 2x

output, one ÷2 output; all outputs are TTL-compatible

? 3-State outputs

? Output skew < 350ps (max.)

? Duty cycle distortion < 500ps (max.)

? Part-to-part skew: 1ns (from tPD max. spec)

? 32/–16mA drive at CMOS output voltage levels

? VCC = 3.3V ± 0.3V

? Inputs can be driven by 3.3V or 5V components

? Available in 28 pin PLCC, LCC and SSOP packages

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
IDT
23+
20CERDIP
9526
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IDT
QQ咨詢(xún)
CDIP
857
全新原裝 研究所指定供貨商
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IDT
5962
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IDT
19+
CDIP
2539
原廠代理渠道,每一顆芯片都可追溯原廠;
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IDT
2122+
CDIP
11190
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詢(xún)價(jià)
IDT
2020+
CDIP
80000
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開(kāi)13%增
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IDT
22+
CDIP
11190
原裝正品
詢(xún)價(jià)
IDT
23+
CDIP
8000
專(zhuān)注配單,只做原裝進(jìn)口現(xiàn)貨
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IDT
23+
CDIP
8000
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ADI
CDIP8
6850
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