IDT54FCT88915TT55J中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION:

The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting in essentially delay across the device. The PLL consists of the phase/frequency detector, charge pump, loop filter and VCO. The VCO is designed for a 2Q operating frequency range of 40MHz to f2Q Max.

FEATURES:

? 0.5 MICRON CMOS Technology

? Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH)

? Max. output frequency: 133MHz

? Pin and function compatible with MC88915T

? 5 non-inverting outputs, one inverting output, one 2x output, one ÷2 output; all outputs are TTL-compatible

? 3-State outputs

? Output skew < 500ps (max.)

? Duty cycle distortion < 500ps (max.)

? Part-to-part skew: 1ns (from tPD max. spec)

? TTL level output voltage swing

? 64/–15mA drive at TTL output voltage levels

? Available in 28 pin PLCC, LCC and SSOP packages