IDT70P247中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

Description

The IDT70P257/247 is a very low power 8K/4K x 16 Dual-Port Static RAM. The IDT70P257/247 is designed to be used as a stand-alone 128/64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual Port SRAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled byCE permits the on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 27mW of power.

The IDT70P257/247 is packaged in a 100 ball 0.5mm- pitch Ball Grid Array. The package is a 1mm thick and designed to fit in wireless handset applications.

Features

◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location

◆ High-speed access

– Industrial: 55ns (max.)

◆ Low-power operation

IDT70P257/247L

Active: 27mW (typ.)

Standby: 3.6μW (typ.)

◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility

◆ IDT70P257/247 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device

◆ M/S = VDD for BUSY output flag on Master

M/S = VSS for BUSY input on Slave

◆ Input Read Register

◆ Output Drive Register

◆ BUSY and Interrupt Flag

◆ On-chip port arbitration logic

◆ Full on-chip hardware support of semaphore signaling between ports

◆ Fully asynchronous operation from either port

◆ LVTTL-compatible, single 1.8V (±100mV) power supply

◆ Available in 100 Ball 0.5mm-pitch BGA

◆ Industrial temperature range (-40°C to +85°C)