IDT71215中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION:

The IDT71215 is a 245,760-bit Cache Tag StaticRAM, organized 16K x 15 and designed to support the Pentium and other Intel processors at bus speeds up to 66MHz. There are twelve common I/O TAG bits, with the remaining three bits used as status bits. A 12-bit comparator is on-chip to allow fast comparison of the twelve stored TAG bits and the current Tag input data. An active HIGH MATCH output is generated when these two groups of data are the same for a given address.

This high-speed MATCH signal, with tADM as fast as 8ns, provides the fastest possible enabling of secondary cache accesses.

FEATURES:

? 16K x 15 Configuration

– 12 TAG Bits

– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)

? Match output uses Valid bit to qualify MATCH output

? High-Speed Address-to-Match comparison times

– 8/9/10/12ns over commercial temperature range

? BRDY circuitry included inside the Cache-Tag for highest

speed operation

? Asynchronous Read/Match operation with Synchronous

Write and Reset operation

? Separate WE for the TAG bits and the Status bits

? Separate OE for the TAG bits, the Status bits, and BRDY

? Synchronous RESET pin for invalidation of all Tag entries

? Dual Chip selects for easy depth expansion with no

performance degredation

? I/O pins both 5V TTL and 3.3V LVTTL compatible with VCCQ pins

? PWRDN pin to place device in low-power mode

? Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP)