IDT71B74S10Y中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION:

The IDT71B74 is a high-speed cache address comparator subsystem consisting of a 65,536-bit static RAM organized as 8K x 8 and an 8-bit comparator. A single IDT71B74 can map 8K cache words into a 2 megabyte address space by using the 21 bits of address organized with the 13 LSBs for the cache address bits and the 8 higher bits for cache data bits. Two IDT71B74s can be combined to provide 29 bits of address comparison, etc.

FEATURES:

? High-speed address to MATCH comparison time

— Commercial: 8/10/12/15/20ns (max.)

? High-speed address access time

— Commercial: 8/10/12/15/20ns (max.)

? High-speed chip select access time

— Commercial: 6/7/8/10ns (max.)

? Power-ON Reset Capability

? Low power consumption

— 830mW (typ.) for 12ns parts

— 880mW (typ.) for 10ns parts

— 920mW (typ.) for 8ns parts

? Produced with advanced BiCMOS high-performance technology

? Input and output directly TTL-compatible

? Standard 28-pin plastic DIP and 28-pin SOJ (300 mil)