IDT71V3557SA80PFI中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

Description

The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround.

Features

◆ 128K x 36, 256K x 18 memory configurations

◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access)

◆ ZBTTM Feature - No dead cycles between write and read cycles

◆ Internally synchronized output buffer enable eliminates the need to control OE

◆ Single R/W (READ/WRITE) control pin

◆ 4-word burst capability (Interleaved or linear)

◆ Individual byte write (BW1 - BW4) control (May tie active)

◆ Three chip enables for simple depth expansion

◆ 3.3V power supply (±5), 3.3V (±5) I/O Supply (VDDQ)

◆ Optional Boundary Scan JTAG Interface (IEEE 1149.1 complaint)

◆ Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA)