DESCRIPTION:

The IDT71V509 is a 3.3V high-speed 1,024,576-bit synchronous SRAM organized as 128K x 8. It is designed to eliminate dead cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBT?, or Zero Bus Turnaround?.

FEATURES:

? 128K x 8 memory configuration

? High speed - 66 MHz (9 ns Clock-to-Data Access)

? Flow-Through Output

? No dead cycles between Write and Read Cycles

? Low power deselect mode

? Single 3.3V power supply (±5)

? Packaged in 44-lead SOJ