IDT72274中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION:

The IDT72264/72274 are monolithic, CMOS, high capacity, high speed, low power first-in, first-out (FIFO) memories with clocked read and write controls. These FIFOs have three main features that distinguish them among SuperSync FIFOs:

First, the data path width can be changed from 9-bits to 18-bits; as a result, halving the depth. A pin called Memory Array Select (MAC) chooses between the two options. This feature helps reduce the need for redesigns or multiple versions of PC cards, since a single layout can be used for both data bus widths.

FEATURES:

? Select 8192 x 18 or 16384x 9 organization (IDT72264)

? Select 16384 x 18 or 32678 x 9 organization (IDT72274)

? Flexible control of read and write clock frequencies

? Reduced dynamic power dissipation

? Auto power down minimizes power consumption

? 15 ns read/write cycle time (10 ns access time)

? Retransmit Capability

? Master Reset clears entire FIFO, Partial Reset clears data, but retains programmable settings

? Empty, full and half-full flags signal FIFO status

? Programmable almost empty and almost full flags, each flag can default to one of two preselected offsets

? Program partial flags by either serial or parallel means

? Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)

? Easily expandable in depth and width

? Independent read and write clocks (permits simultaneous reading and writing with one clock signal)

? Available in the 64-pin Thin Quad Flat Pack (TQFP), 64- pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin Pin Grid Array (PGA)

? Output enable puts data outputs into high impedance

? High-performance submicron CMOS technology

? Industrial temperature range (-40OC to +85OC) is available, tested to military electrical specifications