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IDT72T3665L5BB規(guī)格書詳情
DESCRIPTION:
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/72T36125 are exceptionally deep, extrememly high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits:
? Flexible x36/x18/x9 Bus-Matching on both read and write ports
? A user selectable MARK location for retransmit
? User selectable I/O structure for HSTL or LVTTL
? Asynchronous/Synchronous translation on the read or write ports
? The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
? High density offerings up to 9 Mbit
Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.
FEATURES:
? Choose among the following memory organizations:
IDT72T3645 ― 1,024 x 36
IDT72T3655 ― 2,048 x 36
IDT72T3665 ― 4,096 x 36
IDT72T3675 ― 8,192 x 36
IDT72T3685 ― 16,384 x 36
IDT72T3695 ― 32,768 x 36
IDT72T36105 ― 65,536 x 36
IDT72T36115 ― 131,072 x 36
IDT72T36125 ― 262,144 x 36
? Up to 225 MHz Operation of Clocks
? User selectable HSTL/LVTTL Input and/or Output
? 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
? 3.3V Input tolerant
? Read Enable & Read Clock Echo outputs aid high speed operation
? User selectable Asynchronous read and/or write port timing
? Mark & Retransmit, resets read pointer to user marked position
? Write Chip Select (WCS) input enables/disables Write operations
? Read Chip Select (RCS) synchronous to RCLK
? Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
? Program programmable flags by either serial or parallel means
? Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags
? Separate SCLK input for Serial programming of flag offsets
? User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
? Big-Endian/Little-Endian user selectable byte representation
? Auto power down minimizes standby power consumption
? Master Reset clears entire FIFO
? Partial Reset clears data, but retains programmable settings
? Empty, Full and Half-Full flags signal FIFO status
? Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)
? Output enable puts data outputs into high impedance state
? JTAG port, provided for Boundary Scan function
? Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm) Plastic Ball Grid Array (PBGA)
? Easily expandable in depth and width
? Independent Read and Write Clocks (permit reading and writing simultaneously)
? High-performance submicron CMOS technology
? Industrial temperature range (–40°C to +85°C) is available
產(chǎn)品屬性
- 型號:
IDT72T3665L5BB
- 功能描述:
IC FIFO 4096X36 5NS 208-BGA
- RoHS:
否
- 類別:
集成電路(IC) >> 邏輯 - FIFO
- 系列:
72T
- 標(biāo)準(zhǔn)包裝:
15
- 系列:
74F
- 功能:
異步
- 存儲容量:
256(64 x 4)
- 數(shù)據(jù)速率:
-
- 訪問時(shí)間:
-
- 電源電壓:
4.5 V ~ 5.5 V
- 工作溫度:
0°C ~ 70°C
- 安裝類型:
通孔
- 封裝/外殼:
24-DIP(0.300,7.62mm)
- 供應(yīng)商設(shè)備封裝:
24-PDIP
- 包裝:
管件
- 其它名稱:
74F433
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
IDT |
21+ |
208PBGA |
13880 |
公司只售原裝,支持實(shí)單 |
詢價(jià) | ||
IDT |
23+ |
BGA |
98900 |
原廠原裝正品現(xiàn)貨!! |
詢價(jià) | ||
IDT |
23+ |
BGA |
10000 |
原廠授權(quán)一級代理,專業(yè)海外優(yōu)勢訂貨,價(jià)格優(yōu)勢、品種 |
詢價(jià) | ||
IDT |
22+ |
208PBGA |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價(jià) | ||
IDT |
1922+ |
BGA |
8200 |
萊克訊原廠貨源每一片都來自原廠原裝現(xiàn)貨薄利多 |
詢價(jià) | ||
IDT |
23+ |
NA |
19960 |
只做進(jìn)口原裝,終端工廠免費(fèi)送樣 |
詢價(jià) | ||
IDT |
24+ |
BGA |
96880 |
只做原裝,歡迎來電資詢 |
詢價(jià) | ||
IDT |
23+ |
208PBGA |
9000 |
原裝正品,支持實(shí)單 |
詢價(jià) |