IDT72V275中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES:

? Choose among the following memory organizations:

IDT72V275 32,768 x 18

IDT72V285 65,536 x 18

? Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs

? 10ns read/write cycle time (6.5ns access time)

? Fixed, low first word data latency time

? Auto power down minimizes standby power consumption

? Master Reset clears entire FIFO

? Partial Reset clears data, but retains programmable

settings

? Retransmit operation with fixed, low first word data

latency time

? Empty, Full and Half-Full flags signal FIFO status

? Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

? Program partial flags by either serial or parallel means

? Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

? Output enable puts data outputs into high impedance state

? Easily expandable in depth and width

? Independent Read and Write clocks (permit reading and writing

simultaneously)

? Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin

Slim Thin Quad Flat Pack (STQFP)

? High-performance submicron CMOS technology

? Industrial temperature range (-40°C to +85°C) is available

? Green parts are available, see ordering information