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IDT72V3696L10PF中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

IDT72V3696L10PF
廠商型號(hào)

IDT72V3696L10PF

功能描述

3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING

文件大小

395.33 Kbytes

頁(yè)面數(shù)量

39 頁(yè)

生產(chǎn)廠商 Integrated Device Technology, Inc.
企業(yè)簡(jiǎn)稱(chēng)

IDT

中文名稱(chēng)

Integrated Device Technology, Inc.官網(wǎng)

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數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-1-7 17:09:00

IDT72V3696L10PF規(guī)格書(shū)詳情

DESCRIPTION

The IDT72V3686/72V3696/72V36106 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are a monolithic, high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port SRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO data can be read out of Port B and written into Port C using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations.

FEATURES

? Memory storage capacity:

IDT72V3686 – 16,384 x 36 x 2

IDT72V3696 – 32,768 x 36 x 2

IDT72V36106 – 65,536 x 36 x 2

? Clock frequencies up to 100 MHz (6.5ns access time)

? Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits)

? 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C

? Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRC flag functions)

? Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1024)

? Serial or parallel programming of partial flags

? Big- or Little-Endian format for word and byte bus sizes

? Loopback mode on Port A

? Retransmit Capability

? Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings

? Mailbox bypass registers for each FIFO

? Free-running CLKA, CLKB and CLKC may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)

? Auto power down minimizes power dissipation

? Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

? Pin compatible to the lower density parts, IDT72V3626/72V3636/ 72V3646/72V3656/72V3666/72V3676

? Industrial temperature range (–40°C to +85°C) is available

產(chǎn)品屬性

  • 型號(hào):

    IDT72V3696L10PF

  • 功能描述:

    IC FIFO 131X18 10NS 128QFP

  • RoHS:

  • 類(lèi)別:

    集成電路(IC) >> 邏輯 - FIFO

  • 系列:

    72V

  • 標(biāo)準(zhǔn)包裝:

    15

  • 系列:

    74F

  • 功能:

    異步

  • 存儲(chǔ)容量:

    256(64 x 4)

  • 數(shù)據(jù)速率:

    -

  • 訪問(wèn)時(shí)間:

    -

  • 電源電壓:

    4.5 V ~ 5.5 V

  • 工作溫度:

    0°C ~ 70°C

  • 安裝類(lèi)型:

    通孔

  • 封裝/外殼:

    24-DIP(0.300,7.62mm)

  • 供應(yīng)商設(shè)備封裝:

    24-PDIP

  • 包裝:

    管件

  • 其它名稱(chēng):

    74F433

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