IDT72V825中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION:

The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide synchronous (clocked) First-in, First-out (FIFO) memories designed to run off a 3.3V supply for exceptionally low power consumption. One dual IDT72V805/72V815/72V825/72V835/72V845 device is functionally equivalent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls.

FEATURES:

? The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs

? The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs

? The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs

? The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs

? The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs

? Offers optimal combination of large capacity (8K), high speed, design flexibility, and small footprint

? Ideal for the following applications:

– Network switching

– Two level prioritization of parallel data

– Bidirectional data transfer

– Bus-matching between 18-bit and 36-bit data paths

– Width expansion to 36-bit per package

– Depth expansion to 8,192 words per package

? 10 ns read/write cycle time

? 5V input tolerant

? IDT Standard or First Word Fall Through timing

? Single or double register-buffered Empty and Full Flags

? Easily expandable in depth and width

? Asynchronous or coincident Read and Write Clocks

? Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings

? Half-Full flag capability

? Output enable puts output data bus in high-impedance state

? High-performance submicron CMOS technology

? Available in a 128-pin thin quad flatpack (TQFP)

? Industrial temperature range (–40°C to +85°C) is available