IDT74ALVC125PY中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION:

This quadruple bus buffer gate is built using advanced dual metal CMOS technology. The ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

The ALVC125 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance

FEATURES:

– 0.5 MICRON CMOS Technology

– ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

– VCC = 3.3V ± 0.3V, Normal Range

– VCC = 2.7V to 3.6V, Extended Range

– VCC = 2.5V ± 0.2V

– CMOS power levels (0.4μ W typ. static)

– Rail-to-Rail output swing for increased noise margin

– Available in SOIC, SSOP and TSSOP packages

Drive Features for ALVC125:

– High Output Drivers: ±24mA

– Suitable for heavy loads

APPLICATIONS:

? 3.3V High Speed Systems

? 3.3V and lower voltage computing systems