IDT74ALVC162835PA中文資料IDT數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION:

This 18-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch flip-flop on the low-to-high transition of CLK. WhenOEis high, the outputs are in the high-impedance state. The ALVC162835 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels.

FEATURES:

? 0.5 MICRON CMOS Technology

? Typical tSK(o) (Output Skew) < 250ps

? ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

? VCC = 3.3V ± 0.3V, Normal Range

? VCC = 2.7V to 3.6V, Extended Range

? VCC = 2.5V ± 0.2V

? CMOS power levels (0.4μ W typ. static)

? Rail-to-Rail output swing for increased noise margin

? Available in TSSOP and TVSOP packages

DRIVE FEATURES:

? Balanced Output Drivers: ±12mA

? Low switching noise

APPLICATIONS:

? SDRAM Modules

? PC Motherboards

? Workstations