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IDT74FCT3932-100PA中文資料IDT數(shù)據(jù)手冊(cè)PDF規(guī)格書

IDT74FCT3932-100PA
廠商型號(hào)

IDT74FCT3932-100PA

功能描述

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

文件大小

131.26 Kbytes

頁面數(shù)量

9

生產(chǎn)廠商 Integrated Device Technology, Inc.
企業(yè)簡(jiǎn)稱

IDT

中文名稱

Integrated Device Technology, Inc.官網(wǎng)

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更新時(shí)間

2025-1-14 10:38:00

IDT74FCT3932-100PA規(guī)格書詳情

DESCRIPTION:

The FCT3932 uses phase-lock loop technology to lock the frequency and phase of the feedback to the input reference clock. It provides a large number of low skew outputs that are configurable in 16 different modes using the CNTRL 1-4 inputs.

FEATURES:

? 0.5 MICRON CMOS Technology

? Guaranteed low skew

? 16 programmable frequency configurations

? 17 3-state outputs: ±24 mA FCT3932 ±8 mA FCT32932

? Output configuration:

BANK1: 4 outputs

BANK2: 8 outputs

BANK3: 5 outputs

? Dedicated feedback output (Q_FB)

? Maximum output frequency: 100MHz

? VCC = 3.3V ±0.3V

? Inputs can be driven from 3.3V or 5V components

? Available in 48 SSOP, TSSOP packages

? Suited to SDRAM applications

APPLICATIONS:

SDRAM DIMM Clock, Caches, high speed microprocessors, motherboard clock distribution to DIMMs.

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