IDT74SSTUAE32866ABFG8中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

designed for 1.425V to 1.575V VDD operation.

The control inputs are LVCMOS. All outputs are 1.5-V

CMOS drivers that have been optimized to drive the DDR-II

DIMM load. IDT74SSTUAE32866A operates from a

differential clock (CLK and CLK). Data are registered at the

crossing of CLK going high, and CLK going low.

The C0 input controls the pinout configuration of the 1:2

pinout from A configuration (when low) to B configuration

(when high). The C1 input controls the pinout configuration

from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).

A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0,

C12 = 1)

Parity that arrives one cycle after the data input to which it

applies is checked on the PAR_IN of the first register. The

second register produces to PPO and QERR signals. The

QERR of the first register is left floating. The valid error

information is latched on the QERR output of the second

register. If an error occurs QERR is latched low for two

cycles or until RESET is low.

Features

? Supports 1.5V VDD operation for DDR2 DIMMs

? 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check

functionality

? Supports LVCMOS switching levels on C0, C1, and

RESET inputs

? Low voltage operation: VDD = 1.425V to 1.575V

? Available in 96-ball LFBGA package