IMX8MNCEC中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

Feature

Cortex?-A53 MPCore platform

Quad symmetric Cortex? -A53 processors

? 32 KB L1 Instruction Cache

? 32 KB L1 Data Cache

? Media Processing Engine (MPE) with Arm? NEONTM technology supporting the

Advanced Single Instruction Multiple Data architecture:

? Floating Point Unit (FPU) with support of the Arm? VFPv4-D16 architecture

Support of 64-bit Arm?v8-A architecture

512 KB unified L2 cache

Cortex?-M7 core platform

Low power microcontroller available for customer application:

? low power standby mode

? IoT features including Weave

? Manage IR or wireless remote

? ML inference applications (enhanced for i.MX 8M Nano)

Cortex? M7 CPU:

? 256 KB tightly coupled memory (TCM)

Connectivity

One USB 2.0 OTG controllers with integrated PHY interfaces:

? Spread spectrum clock support

Three Ultra Secure Digital Host Controller (uSDHC) interfaces:

? MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec

? SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100

MB/sec

? Support for SDXC (extended capacity)

One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),

Ethernet AVB, and IEEE 1588

Four Universal Asynchronous Receiver/Transmitter (UART) modules

Four I2C modules

Three SPI modules

On-chip memory

Boot ROM (256 KB)

On-chip RAM (512 KB + 32 KB)

GPIO and pin multiplexing

General-purpose input/output (GPIO) modules with interrupt capability

Input/output multiplexing controller (IOMUXC) to provide centralized pad control

Power management

Temperature sensor with programmable trip points

Flexible power domain partitioning with internal power switches to support efficient

power management

External memory interface

16-bit DRAM interfaces:

? LPDDR4-3200

? DDR4-2400

? DDR3L-1600

8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to

62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200

MB/sec)

eMMC 5.1 Flash (3 interfaces)

SPI NOR Flash (3 interfaces)

QuadSPI Flash with support for XIP (for Cortex?-M7 in low-power mode) and parallel

read mode of two identical FLASH devices

Multimedia

Graphic Processing Unit:

? GC7000UL with OpenCL and Vulkan support

? 2 shader

? 99.8 million triangles/sec

? 0.6 giga pixel/sec

? 9.6 GFLOPs 32-bit/19.2 GFLOPs 16-bit

? Supports OpenGL ES 1.1, 2.0, 3.0, OpenCL

? Core clock frequency of 600 MHz

? Shader clock frequency of 600 MHz

LCDIF Display Controller:

? Support up to 1080p60 display through MIPI DSI

MIPI Interfaces:

? 4-lane MIPI DSI interface

? 4-lane MIPI CSI interface

Audio:

? S/PDIF input and output, including a raw capture input mode

? Five external synchronous audio interface (SAI) modules supporting I2S, AC97,

TDM, codec/DSP, and DSD interfaces, comprising one SAI with 4 Tx and 4 Rx

lanes, two SAI with 2 Tx and 2 Rx lanes, and two SAI with 1 Tx and 1Rx lane. All

ports support 49.152 MHz BCLK.

? ASRC supports processing 32 audio channels, 4 context groups, 8 kHz to 384 kHz

sample rate and 1/16 to 8x sample rate conversion ratio.

? Pulse Density Modulation (PDM) input

Security

Resource Domain Controller (RDC):

? supports 4 domains and up to 8 regions of DDR

Arm? TrustZone? (TZ) architecture:

? Arm? Cortex-A53 MPCore TrustZone support

On-chip RAM (OCRAM) secure region protection using OCRAM controller

High Assurance Boot (HAB)

Cryptographic acceleration and assurance module (CAAM):

? Support Widevine and PlayReady content protection

? Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms

? Real-time integrity checker (RTIC)

? DRM support for RSA, AES, 3DES, DES

? Side channel attack resistance

? True random number generation (RNG)

? Manufacturing protection support

Secure non-volatile storage (SNVS):

? Secure real-time clock (RTC)

Secure JTAG controller (SJC)

System debug

Arm? CoreSightTM debug and trace technology

Trace Port Interface Unit (TPIU) to support off-chip real-time trace

Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering

Unified trace capability for Quad Cortex?-A53 and Cortex?-M7 CPUs

Cross Triggering Interface (CTI)

Support for 4-pin (JTAG) debug interface