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IN74AC533DW規(guī)格書詳情
The IN74AC533 is identical in pinout to the LS/ALS533, HC/HCT533. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs.
These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The data appears as the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high impedance state. Thus, data may be latched even when the outputs are not enabled.
? Outputs Directly Interface to CMOS, NMOS, and TTL
? Operating Voltage Range: 2.0 to 6.0 V
? Low Input Current: 1.0 μA; 0.1 μA @ 25°C
? High Noise Immunity Characteristic of CMOS Devices
? Outputs Source/Sink 24 mA
? 3-State Outputs for Bus Interfacing
產(chǎn)品屬性
- 型號(hào)：
IN74AC533DW
- 制造商：
INTEGRAL
- 制造商全稱：
INTEGRAL
- 功能描述：
Octal 3-State Inverting Transparent Latch High-Speed Silicon-Gate CMOS
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
IKSEMICON |
23+ |
NA |
19960 |
只做進(jìn)口原裝,終端工廠免費(fèi)送樣 |
詢價(jià) | ||
INTEGRAL |
24+ |
原廠封裝 |
2000 |
原裝現(xiàn)貨假一罰十 |
詢價(jià) | ||
MAX/DALL |
2023+環(huán)保現(xiàn)貨 |
標(biāo)準(zhǔn)封裝 |
2500 |
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