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IP101GA集成電路(IC)的驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書PDF中文資料

IP101GA
廠商型號(hào)

IP101GA

參數(shù)屬性

IP101GA 包裝為散裝;類別為集成電路(IC)的驅(qū)動(dòng)器接收器收發(fā)器;產(chǎn)品描述:PHY CHIP (0-80)

功能描述

Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver

文件大小

3.45039 Mbytes

頁(yè)面數(shù)量

65 頁(yè)

生產(chǎn)廠商 List of Unclassifed Manufacturers
企業(yè)簡(jiǎn)稱

ETC

中文名稱

未分類制造商

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2025-1-9 8:01:00

IP101GA規(guī)格書詳情

Features

10/100Mbps IEEE 802.3/802.3u compliant

Fast Ethernet transceiver

Supports 100Base-TX/FX Media Interface

Supports MII/ RMII Interface

Supports Auto MDI/MDIX function

Power Management Tool

- APS, auto power saving while Link-off

- 802.3az, protocol based power saving

- WOL+, light traffic power saving

- PWD, force-off power saving

- Supports MII with LPI for RX and TX

- Supports RMII with LPI for RX

Supports Base Line Wander compensation

Supports Interrupt function

Built in synchronization FIFO to support

jumbo frame size up to 12KB in MII mode (10KB

in RMII 100Mbps mode)

Supports MDC and MDIO to communicate

with the MAC

EMI Management Tool

- F/W based control

- 4 levels for mapping the difference layout

length on the PCB

Single 3.3V power supply

Built-in Vcore regulator

DSP-based PHY Transceiver technology

System Debug Assistant Tool

- 16 bit RX counter

- 9 bit RXError/CRC counter

- Isolate MII/RMII

- RX to TX Loopback

- Loopback MII/RMII

Using either 25MHz crystal/oscillator or

50MHz oscillator REF_CLK as clock source

Built-in 49.9ohm resistors for simplifying

BOM

Flexible LED display

Process: 85nm

Application

NAS

Network Printers and Servers

IP Set-Top Box

IP/Smart TV

General Description

IP1

IP1

IP1

IP1

Package and operation temperature

01G: dice, 0~70℃

01GA: 48LQFP, 0~70℃

01GR: 32QFN, 0~70℃

01GRI: 32QFN, -40~85℃

IP101G is an IEEE 802.3/802.3u compliant

single-port Fast Ethernet Transceiver for both

100Mbps and 10Mbps operations. It supports

Auto MDI/MDIX function to simplify the network

installation and reduce the system maintenance

cost. To improve the system performance,

IP101G provides a hardware interrupt pin to

indicate the link, speed and duplex status

change. IP101G provides Media Independent

Interface (MII) or Reduced Media Independent

Interface (RMII) to connect with different types

of 10/100Mbps Media Access Controller (MAC).

IP101G is designed to use category 5

unshielded twisted-pair cable or Fiber-Optic

cables connecting to other LAN devices. A

PECL interface is supported to connect with an

external 100Base-FX fiber optical transceiver.

Except good performance, reliability, rich power

saving method and extreme low operating

current, IP101G provides a serial tool for

system designers to complete their projects

easily. They are System Debug Assistant Tool

and EMI Management Tool.

IP101G is fabricated with advanced CMOS

(85nm) technology and design is based on

IC Plus’s 5th Ethernet-PHY architecture, this

feature makes IP101G consumes very low

power. Such as in the full load operation

(100Mbps_FDX), it only takes below 0.15W.

IP101GA / IP101GR&IP101GRI are available in

48LQFP/32QFN, lead-free package.

EMIMT: Patent under apply.

Game console

IP and Video Phone

PoE

Telecom Fiber device

產(chǎn)品屬性

  • 產(chǎn)品編號(hào):

    IP101GA

  • 制造商:

    WIZnet

  • 類別:

    集成電路(IC) > 驅(qū)動(dòng)器,接收器,收發(fā)器

  • 包裝:

    散裝

  • 描述:

    PHY CHIP (0-80)

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IC+(九陽(yáng)電子)
23+
LQFP48(7x7)
6000
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ICPLUS
2226+
LQFP48
5828
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ICPLUS
2018+
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6000
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PLUS
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NA/
3350
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45000
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1356
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7200
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