IS42S16400A中文資料北京矽成數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

OVERVIEW

ISSIs 64Mb Synchronous DRAM IS42S16400A is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance.The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

FEATURES

? Clock frequency:166, 133, 100 MHz

? Fully synchronous; all signals referenced to a positive clock edge

? Internal bank for hiding row access/precharge

? Single 3.3V power supply

? LVTTL interface

? Programmable burst length – (1, 2, 4, 8, full page)

? Programmable burst sequence: Sequential/Interleave

? Self refresh modes

? 4096 refresh cycles every 64 ms

? Random column address every clock cycle

? Programmable CAS latency (2, 3 clocks)

? Burst read/write and burst read/single write operations capability

? Burst termination by burst stop and precharge command

? Byte controlled by LDQM and UDQM

? Industrial temperature availability (133MHz, 100MHz)

? Package: 400-mil 54-pin TSOP II, a lead-free package is available.