IS42S32200-7TI中文資料北京矽成數(shù)據(jù)手冊PDF規(guī)格書

OVERVIEW

ISSIs 64Mb Synchronous DRAM IS42S32200 is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

GENERAL DESCRIPTION

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits.

FEATURES

? Clock frequency: 166, 143 MHz

? Fully synchronous; all signals referenced to a positive clock edge

? Internal bank for hiding row access/precharge

? Single 3.3V power supply

? LVTTL interface

? Programmable burst length – (1, 2, 4, 8, full page)

? Programmable burst sequence: Sequential/Interleave

? Self refresh modes

? 4096 refresh cycles every 64 ms

? Random column address every clock cycle

? Programmable CAS latency (2, 3 clocks)

? Burst read/write and burst read/single write operations capability

? Burst termination by burst stop and precharge command

? Industrial temperature availability

? Package 400-mil 86-pin TSOP II