IS46LQ16512A中文資料北京矽成數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

FEATURES

? Configuration

- 512Mb x16 x 1 channel

- 8 internal banks

? Low-voltage Core and I/O Power Supplies

VDD1 = 1.70-1.95V

VDD2 = 1.06-1.17V

VDDQ = 1.06-1.17V (LPDDR4)

VDDQ = 0.57-0.65V (LPDDR4X)

?LVSTL(Low Voltage Swing Terminated Logic) I/O

Interface

? Internal VREF and VREF Training

? Dynamic ODT :

DQ ODT :VSSQ Termination

CA ODT :VSS Termination

? Max. Clock Frequency : 1866MHz (3733Mbps)

? 16n Pre-fetch DDR architecture

? Single data rate (multiple cycles) command/

address bus

? Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

? Programmable burst lengths (16 or 32)

? ZQ Calibration

? Operation

? Clock-Stop capability

Temperature

Industrial (T C = -40°C to 95°C)

Automotive, A1 (TC = -40°C to 95°C)

Automotive, A2 (TC = -40°C to 105°C)

Automotive, A3 (TC = -40°C to 125°C)

DESCRIPTION

The IS43/46LQ16512A and IS43/46LQ16512AL are

8Gbit CMOS LPDDR4 SDRAM. The device is organized as 1 channel per device, and each channel is

8-banks and 16-bits. This product uses a doubledata-rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 16N

prefetch architecture with an interface designed to

transfer two data words per clock cycle at the I/O pins.

This product offers fully synchronous operations

referenced to both rising and falling edges of the clock.

The data paths are internally pipelined and 16n bits

prefetched to achieve very high bandwidth.

? On-chip temperature sensor whose status

can be read from MR4

? 200-ball x16 BGA Package ( 10x14.5 mm) in Green Package