IS61NP12832-133B中文資料北京矽成數據手冊PDF規(guī)格書

DESCRIPTION

The 4 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 words by 18 bits, fabricated with ISSIs advanced CMOS technology.

FEATURES

? 100 percent bus utilization

? No wait cycles between Read and Write

? Internal self-timed write cycle

? Individual Byte Write Control

? Single R/W (Read/Write) control pin

? Clock controlled, registered address, data and control

? Interleaved or linear burst sequence control using MODE input

? Three chip enables for simple depth expansion and address pipelining for TQFP

? Power Down mode

? Common data inputs and data outputs

? CKE pin to enable clock and suspend operation

? JEDEC 100-pin TQFP, 119 PBGA package

? Single +3.3V power supply (± 5)

? NP Version: 3.3V I/O Supply Voltage

? NLP Version: 2.5V I/O Supply Voltage

? Industrial temperature available