IS61NVVP51236-250B中文資料北京矽成數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The 16 Meg NVVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 256K words by 72 bits, 512K words by 36 bits and are fabricated with ISSIs advanced CMOS technology.

FEATURES

? 100 percent bus utilization

? No wait cycles between Read and Write

? Internal self-timed write cycle

? Individual Byte Write Control

? Single R/W (Read/Write) control pin

? Clock controlled, registered address, data and control

? Interleaved or linear burst sequence control using MODE input

? Power Down mode

? Common data inputs and data outputs

? CKE pin to enable clock and suspend operation

? JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages

? Single +1.8V (± 5) power supply

? JTAG Boundary Scan

? Industrial temperature available