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IS61SP6464-7TQ中文資料北京矽成數(shù)據(jù)手冊PDF規(guī)格書
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DESCRIPTION
The ISSI IS61SP6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high performance, secondary cache for the i486?, Pentium?, 680X0?, and PowerPC? microprocessors. It is organized as 65,536 words by 64 bits, fabricated with ISSIs advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
FEATURES
? Fast access time:
– 133, 117, 100 MHz; 6 ns (83 MHz);
7 ns (75 MHz); 8 ns (66 MHz)
? Internal self-timed write cycle
? Individual Byte Write Control and Global Write
? Clock controlled, registered address, data and control
? Pentium? or linear burst sequence control using MODE input
? Five chip enables for simple depth expansion and address pipelining
? Common data inputs and data outputs
? Power-down control by ZZ input
? JEDEC 128-Pin TQFP 14mm x 20mm package
? Single +3.3V power supply
? Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ or VCCQ to alter their power-up state