ISLA224S20IR1Z集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

The ISLA224S is a series of low-power, high-performance,

dual-channel 14-bit, analog-to-digital converters. Designed

with FemtoCharge? technology on a standard CMOS process,

the series supports sampling rates of up to 250MSPS. The

ISLA224S is part of a pin-compatible family of 12- and 14-bit

dual-channel A/Ds with maximum sample rates ranging from

125MSPS to 250MSPS and shares the same analog core as

Intersil's proven ISLA224P series of ADCs. The family

minimizes power consumption while providing state-of-the art

dynamic performance, offering an optimal performance-vspower trade-off.

Differentiating the ISLA224S from the ISLA224P is its highly

configurable, JESD204B-compliant, high speed serial output

link. The link offers data rates up to 4.375Gbps per lane and

multiple packing modes. It can be configured to use two or

three lanes to transmit the conversion data, allowing for

flexibility in the receiver design. The SERDES transmitter also

provides deterministic latency and multi-chip time alignment

support to satisfy an application's complex synchronization

requirements.

A serial peripheral interface (SPI) port allows for extensive

configurability of the JESD204B transmitter including access

to its built-in link and transport-layer test patterns. The SPI port

also provides control for numerous additional features

including the fine gain and offset adjustments of the two ADC

cores as well as the programmable clock divider, enabling 2x

and 4x harmonic clocking.

The ISLA224S is available in a space-saving 7mmx7mm 48 Ld

QFN package. The package features a thermal pad for

improved thermal performance and is specified over the full

industrial temperature range (-40°C to +85°C).

Features

? JESD204A/B High Speed Data Interface

- JESD204A Compliant

- JESD204B Device Subclass 0 Compliant

- JESD204B Device Subclass 2 Compatible

- Up to 3 JESD204 Output Lanes Running up to 4.375Gbps

- Highly Configurable JESD204 Transmitter

? Multiple Chip Time Alignment and Deterministic Latency

Support (JESD204B Device Subclass 2)

? SPI Programmable Debugging Features and Test Patterns

? 48-pin QFN 7mmx7mm Package

Applications

? Radar and Satellite Antenna Array Processing

? Broadband Communications and Microwave Receivers

? High-Performance Data Acquisition

? Communications Test Equipment

? High-Speed Medical Imaging