首頁(yè)>ISPLSI1024EA-125LT100>規(guī)格書詳情
ISPLSI1024EA-125LT100中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書

廠商型號(hào) |
ISPLSI1024EA-125LT100 |
功能描述 | In-System Programmable High Density PLD |
文件大小 |
162.63 Kbytes |
頁(yè)面數(shù)量 |
13 頁(yè) |
生產(chǎn)廠商 | Lattice Semiconductor |
企業(yè)簡(jiǎn)稱 |
Lattice【萊迪思】 |
中文名稱 | 萊迪思半導(dǎo)體公司官網(wǎng) |
原廠標(biāo)識(shí) | ![]() |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-5-16 11:21:00 |
人工找貨 | ISPLSI1024EA-125LT100價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
相關(guān)芯片規(guī)格書
更多- ISPLSI1024-60LH/883
- ISPLSI1024EA-100LT100
- ISPLSI1016E-80LT44I
- ISPLSI1016EA
- ISPLSI1016EA-100LJ44
- ISPLSI1016EA-125LT44
- ISPLSI1016EA-200LJ44
- ISPLSI1016EA-200LT44
- ISPLSI1016EA-100LT44
- ISPLSI1016E-80LT44
- ISPLSI1016EA-125LJ44
- ISPLSI1016EA-125LJ44
- ISPLSI1016EA-200LJ44
- ISPLSI1016EA-125LT44
- ISPLSI1016EA-100LJ44
- ISPLSI1016EA_07
- ISPLSI1016EA
- ISPLSI1016EA-100LT44
ISPLSI1024EA-125LT100規(guī)格書詳情
Description
The ispLSI 1024EA is a High Density Programmable Logic Device containing 144 Registers, 48 Universal I/O pins, two Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP).
Features
? HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 48 I/O Pins, Two Dedicated Inputs
— 144 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
? NEW FEATURES
— 100 IEEE 1149.1 Boundary Scan Testable
— ispJTAG? In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O Supports
MixedVoltage Systems (VCCIO Pin)
— Open-Drain Output Option
? HIGH PERFORMANCE E2CMOS? TECHNOLOGY
— fmax = 200 MHz Maximum Operating Frequency
— tpd = 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
? IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-Market
and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
? OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
? ispDesignEXPERT? – LOGIC COMPILER
AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER?
— PC and UNIX Platforms
產(chǎn)品屬性
- 型號(hào):
ISPLSI1024EA-125LT100
- 功能描述:
CPLD - 復(fù)雜可編程邏輯器件
- RoHS:
否
- 制造商:
Lattice
- 存儲(chǔ)類型:
EEPROM
- 大電池?cái)?shù)量:
128
- 最大工作頻率:
333 MHz
- 延遲時(shí)間:
2.7 ns
- 可編程輸入/輸出端數(shù)量:
64
- 工作電源電壓:
3.3 V
- 最大工作溫度:
+ 90 C
- 最小工作溫度:
0 C
- 封裝/箱體:
TQFP-100
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
LATTICE |
24+ |
TQFP |
21580 |
原裝現(xiàn)貨 |
詢價(jià) | ||
Lattice Semiconductor Corporat |
23+ |
100TQFP |
9000 |
原裝正品,支持實(shí)單 |
詢價(jià) | ||
LATTICE |
24+ |
QFP |
80000 |
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
詢價(jià) | ||
LATTICE/萊迪斯 |
23+ |
PLCC-84P |
10000 |
原廠授權(quán)一級(jí)代理,專業(yè)海外優(yōu)勢(shì)訂貨,價(jià)格優(yōu)勢(shì)、品種 |
詢價(jià) | ||
LATTICE |
23+ |
QFP |
8560 |
受權(quán)代理!全新原裝現(xiàn)貨特價(jià)熱賣! |
詢價(jià) | ||
LATT |
24+ |
QFP |
2250 |
100%全新原裝公司現(xiàn)貨供應(yīng)!隨時(shí)可發(fā)貨 |
詢價(jià) | ||
LATTICE |
25+ |
QFP |
4860 |
品牌專業(yè)分銷商,可以零售 |
詢價(jià) | ||
LATTICE |
23+ |
PLCC-84 |
41972 |
##公司主營(yíng)品牌長(zhǎng)期供應(yīng)100%原裝現(xiàn)貨可含稅提供技術(shù) |
詢價(jià) | ||
Lattice |
2318+ |
QFP-100 |
4980 |
Lattice全系列進(jìn)口原裝特價(jià) |
詢價(jià) | ||
LATTICE |
1948+ |
QFP |
6852 |
只做原裝正品現(xiàn)貨!或訂貨假一賠十! |
詢價(jià) |