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ISPLSI1048EA-100LQ128中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

廠商型號(hào) |
ISPLSI1048EA-100LQ128 |
功能描述 | In-System Programmable High Density PLD |
文件大小 |
182.29 Kbytes |
頁(yè)面數(shù)量 |
14 頁(yè) |
生產(chǎn)廠商 | Lattice Semiconductor |
企業(yè)簡(jiǎn)稱 |
Lattice【萊迪思】 |
中文名稱 | 萊迪思半導(dǎo)體公司官網(wǎng) |
原廠標(biāo)識(shí) | ![]() |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-5-17 22:30:00 |
人工找貨 | ISPLSI1048EA-100LQ128價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
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ISPLSI1048EA-100LQ128規(guī)格書(shū)詳情
Description
The ispLSI 1048EA is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP).
Features
? HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Eight Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally Compatible with ispLSI 1048C and 1048E
? NEW FEATURES
— 100 IEEE 1149.1 Boundary Scan Testable
— ispJTAG? In-System Programmable Via IEEE 1149.1 (JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O supports Mixed Voltage Systems (VCCIO Pin)
— Open Drain Output Option
? HIGH PERFORMANCE E2CMOS? TECHNOLOGY
— fmax = 170 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
? IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
? OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global Interconnectivity
? ispDesignEXPERT? – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER?
— PC and UNIX Platforms
產(chǎn)品屬性
- 型號(hào):
ISPLSI1048EA-100LQ128
- 功能描述:
CPLD - 復(fù)雜可編程邏輯器件
- RoHS:
否
- 制造商:
Lattice
- 存儲(chǔ)類型:
EEPROM
- 大電池?cái)?shù)量:
128
- 最大工作頻率:
333 MHz
- 延遲時(shí)間:
2.7 ns
- 可編程輸入/輸出端數(shù)量:
64
- 工作電源電壓:
3.3 V
- 最大工作溫度:
+ 90 C
- 最小工作溫度:
0 C
- 封裝/箱體:
TQFP-100
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
LATTICE/萊迪斯 |
24+ |
NA |
80000 |
只做自己庫(kù)存,全新原裝進(jìn)口正品假一賠百,可開(kāi)13%增 |
詢價(jià) | ||
LATTICE |
25+23+ |
QFP |
26570 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
LATTICE |
2016+ |
QFP |
4558 |
只做進(jìn)口原裝現(xiàn)貨!假一賠十! |
詢價(jià) | ||
LatticeSemiconductorCorp |
24+ |
128-PQFP(28x28) |
66800 |
原廠授權(quán)一級(jí)代理,專注汽車、醫(yī)療、工業(yè)、新能源! |
詢價(jià) | ||
LATTICE/萊迪斯 |
23+ |
QFP |
3000 |
一級(jí)代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、 |
詢價(jià) | ||
LATTICE |
21+ |
QFP128 |
12588 |
原裝正品,自己庫(kù)存 假一罰十 |
詢價(jià) | ||
Lattice |
2138+ |
QFP |
8960 |
專營(yíng)BGA,QFP原裝現(xiàn)貨,假一賠十 |
詢價(jià) | ||
Lattice Semiconductor Corporat |
22+ |
128TQFP |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價(jià) | ||
LATTICE |
24+ |
FPGA |
5450 |
原裝現(xiàn)貨 |
詢價(jià) | ||
Lattice |
16+ |
TQFP |
2500 |
進(jìn)口原裝現(xiàn)貨/價(jià)格優(yōu)勢(shì)! |
詢價(jià) |