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ISPLSI5384VE-125LF256中文資料萊迪思數(shù)據(jù)手冊PDF規(guī)格書
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ISPLSI5384VE-125LF256規(guī)格書詳情
ispLSI 5000VE Description
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.
Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.
Features
? Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 18000 PLD Gates / 384 Macrocells
— Up to 192 I/O Pins
— 384 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
? HIGH PERFORMANCE E2CMOS? TECHNOLOGY
— fmax = 165 MHz Maximum Operating Frequency
— tpd = 6.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
? IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
? 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
? ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell
產(chǎn)品屬性
- 型號:
ISPLSI5384VE-125LF256
- 功能描述:
CPLD - 復(fù)雜可編程邏輯器件
- RoHS:
否
- 制造商:
Lattice
- 存儲類型:
EEPROM
- 大電池數(shù)量:
128
- 最大工作頻率:
333 MHz
- 延遲時間:
2.7 ns
- 可編程輸入/輸出端數(shù)量:
64
- 工作電源電壓:
3.3 V
- 最大工作溫度:
+ 90 C
- 最小工作溫度:
0 C
- 封裝/箱體:
TQFP-100
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
LATTE/萊迪斯 |
23+ |
NA/ |
23 |
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價 | ||
DIODES |
2022+ |
POWERDI-123 |
6000 |
一級代理/分銷渠道價格優(yōu)勢 十年芯程一路只做原裝正品 |
詢價 | ||
LATTICE |
23+ |
BGA |
28000 |
原裝正品 |
詢價 | ||
LATTICE |
2016+ |
BGA |
6528 |
只做進(jìn)口原裝現(xiàn)貨!或者訂貨,假一賠十! |
詢價 | ||
LATTICE/萊迪斯 |
2023+ |
BGA |
8635 |
一級代理優(yōu)勢現(xiàn)貨,全新正品直營店 |
詢價 | ||
LatticeSemiconductorCorp |
23+ |
256-FPBGA(17x17) |
66800 |
原廠授權(quán)一級代理,專注汽車、醫(yī)療、工業(yè)、新能源! |
詢價 | ||
LATTICE |
NA |
5650 |
一級代理 原裝正品假一罰十價格優(yōu)勢長期供貨 |
詢價 | |||
Lattice Semiconductor Corporat |
23+ |
256-BGA |
11200 |
主營:汽車電子,停產(chǎn)物料,軍工IC |
詢價 | ||
LATTICE |
24+ |
BGA |
23000 |
免費送樣原盒原包現(xiàn)貨一手渠道聯(lián)系 |
詢價 | ||
LATTICE |
23+ |
BGA |
12800 |
##公司主營品牌長期供應(yīng)100%原裝現(xiàn)貨可含稅提供技術(shù) |
詢價 |