IW4027BD中文資料IKSEMICON數(shù)據(jù)手冊(cè)PDF規(guī)格書

The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positive going edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override the J, K, or Clock inputs. The outputs are buffered for best system performance.

· Operating Voltage Range: 3.0 to 18 V

· Maximum input current of 1 mA at 18 V over full package

temperature range; 100 nA at 18 V and 25°C

· Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply