IW4043B中文資料IKSEMICON數(shù)據(jù)手冊PDF規(guī)格書

Quad 3-State R/S Latches

High-Voltage Silicon-Gate CMOS

The IW4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic “1” or high on the ENABLE input connects the latch states to the Q outputs. A logic “0” or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

? Operating Voltage Range: 3.0 to 18 V

? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C

? Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply