KSZ8765CLX_V01中文資料微芯科技數(shù)據(jù)手冊PDF規(guī)格書

Target Applications

? Industrial Ethernet Applications that Employ IEEE

802.3-Compliant MACs. (Ethernet/IP, Profinet,

MODBUS TCP, etc.)

? VoIP Phone

? Set-Top/Game Box

? Automotive

? Industrial Control

? IPTV POF

? SOHO Residential Gateway with Full-Wire Speed

of Four LAN Ports

? Broadband Gateway/Firewall/VPN

? Integrated DSL/Cable Modem

? Wireless LAN Access Point + Gateway

? Standalone 10/100 Switch

? Networked Measurement and Control Systems

Features

? Management Capabilities

- The KSZ8765CLX Includes All the Functions

of a 10/100BASE-T/TX Switch System Which

Combines a Switch Engine, Frame Buffer

Management, Address Look-Up Table,

Queue Management, MIB Counters, Media

Access Controllers (MAC), and PHY Transceivers

- Non-Blocking Store-and-Forward Switch

Fabric Assures Fast Packet Delivery by Utilizing

a 1024-Entries Forwarding Table

- Port Mirroring/Monitoring/Sniffing: Ingress

and/or Egress Traffic to Any Port

- MIB Counters for Fully-Compliant Statistics

Gathering (36 Counters per Port)

- Support Hardware for Port-Based Flush and

Freeze Command in MIB Counter.

- Multiple Loopback of Remote, PHY, and MAC

Modes Support for the Diagnostics

- Rapid Spanning Tree Support (RSTP) for

Topology Management and Ring/LinearRecovery

? Robust PHY Ports

- Four Integrated IEEE 802.3/802.3u-Compliant

Ethernet Transceivers; Port 1 and Port 2

Support 100Base-FX, Port 3 and Port 4 Support

10/100Base-T/TX

- 802.1az EEE Supported

- On-Chip Termination Resistors and Internal

Biasing for Differential Pairs to Reduce

Power

- HP Auto MDI/MDI-X Crossover Support Eliminates

the Need to Differentiate Between

Straight or Crossover Cables in Applications

? MAC and GMAC Ports

- Four Internal Media Access Control (MAC1 to

MAC4) Units and One Internal Gigabit Media

Access Control (GMAC5) Unit

- GMII, RGMII, MII, or RMII Interfaces Support

for the Port 5 GMAC5 with Uplink

- 2 KByte Jumbo Packet Support

- Tail Tagging Mode (One Byte Added Before

FCS) Support on Port 5 to Inform the Processor

in which the Ingress Port Receives the

Packet and its Priority

- Supports Reduced Media Independent Interface

(RMII) with 50 MHz Reference Clock

Output

- Supports Media Independent Interface (MII)

in Either PHY Mode or MAC Mode on Port 5

- LinkMD? Cable Diagnostic Capabilities for

Determining Cable Opens, Shorts, and

Length

? Advanced Switch Capabilities

- Non-Blocking Store-and-Forward Switch

Fabric Assures Fast Packet Delivery by Utilizing

1024 Entry Forwarding Table

- 64 KB Frame Buffer RAM

- IEEE 802.1q VLAN Support for up to 128

Active VLAN Groups (Full-Range 4096 of

VLAN IDs)

- IEEE 802.1p/Q Tag Insertion or Removal on

a Per Port Basis (Egress)

- VLAN ID Tag/Untag Options on Per Port Basis

- Fully Compliant with IEEE 802.3/802.3u Standards

- IEEE 802.3x Full-Duplex with Force-Mode

Option and Half-Duplex Back-Pressure Collision

Flow Control

- IEEE 802.1w Rapid Spanning Tree Protocol

Support

- IGMP v1/v2/v3 Snooping for Multicast Packet

Filtering

- QoS/CoS Packets Prioritization Support:

802.1p, DiffServ-Based and Re-Mapping of

802.1p Priority Field Per Port Basis on Four

Priority Levels

- IPv4/IPv6 QoS Support

- IPV6 Multicast Listener Discovery (MLD)

Snooping

- Programmable Rate Limiting at the Ingress

and Egress Ports on a Per Port Basis

- Jitter-Free Per Packet Based Rate Limiting

Support

- Tail Tag Mode (1 byte Added before FCS)

Support on Port 5 to Inform the Processor

which Ingress Port Receives the Packet

- Broadcast Storm Protection with Percentage

Control (Global and Per Port Basis)

- 1K Entry Forwarding Table with 64 KB Frame

Buffer

- 4 Priority Queues with Dynamic Packet Mapping

for IEEE 802.1P, IPV4 TOS (DIFFSERV),

IPv6 Traffic Class, etc.

- Supports WoL Using AMD’s Magic Packet

- VLAN and Address Filtering

- Supports 802.1x Port-Based Security,

Authentication and MAC-Based Authentication

via Access Control Lists (ACL)

- Provides Port-Based and Rule-Based ACLs

to Support Layer 2 MAC SA/DA Address,

Layer 3 IP Address and IP Mask, Layer 4

TCP/UDP Port Number, IP Protocol, TCP

Flag and Compensation for the Port Security

Filtering

- Ingress and Egress Rate Limit Based on Bit

per Second (bps) and Packet-Based Rate

Limiting (pps)

? Configuration Registers Access

- High-Speed SPI (4-Wire, up to 25 MHz) Interface

to Access All Internal Registers

- MII Management (MIIM, MDC/MDIO 2-Wire)

Interface to Access All PHY Registers per

Clause 22.2.4.5 of the IEEE 802.3 Specification

- I/O Pin Strapping Facility to Set Certain Register

Bits from I/O Pins During Reset Time

- Control Registers Configurable On-the-Fly

? Power and Power Management

- Full-Chip Software Power-Down (All Register

Values are Not Saved and Strap-In value Will

Re-Strap after it Releases the Power-Down)

- Per-Port Software Power-Down

- Energy Detect Power-Down (EDPD), which

Disables the PHY Transceiver When Cables

are Removed

- Supports IEEE P802.3az Energy Efficient

Ethernet (EEE) to Reduce Power Consumption

in Transceivers in LPI State Even

Though Cables are Not Removed

- Dynamic Clock Tree Control to Reduce

Clocking in Areas that are Not in Use

- Low Power Consumption without Extra

Power Consumption on Transformers

- Voltages: Using External LDO Power Supplies

- Analog VDDAT 3.3V or 2.5V

- VDDIO Support 3.3V, 2.5V, and 1.8V

- Low 1.2V Voltage for Analog and Digital Core

Power

- WoL Support with Configurable Packet Control

? Additional Features

- Single 25 MHz +50 ppm Reference Clock

Requirement

- Comprehensive Programmable Two-LED

Indicator Support for Link, Activity, Full-/Half-

Duplex, and 10/100 Speed

? Packaging and Environmental

- Commercial Temperature Range: 0°C to

+70°C

- Industrial Temperature Range: –40°C to

+85°C

- Package Available in an 80-Pin LQFP, Lead-

Free (RoHS-Compliant) Package

- Supports Human Body Model (HBM) ESD Rating of 5 kV

- 0.065 μm CMOS Technology for Lower Power Consumption