L74VHC1GT50DTT3中文資料樂山無線電數(shù)據(jù)手冊PDF規(guī)格書

Noninverting Buffer / CMOS Logic Level Shifter with LSTTL–Compatible Inputs

The L74VHC1GT50 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.

The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power supply.

The L74VHC1GT50 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the L74VHC1GT50 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc.

? High Speed: t PD = 3.5 ns (Typ) at V CC = 5 V

? Low Power Dissipation: I CC= 2 mA (Max) at T A= 25°C

? TTL–Compatible Inputs: V IL= 0.8 V; V IH = 2.0 V

? CMOS–Compatible Outputs: V OH > 0.8 V CC ; V OL < 0.1 V CC @Load

? Power Down Protection Provided on Inputs and Outputs

? Balanced Propagation Delays

? Pin and Function Compatible with Other Standard Logic Families

? Chip Complexity: FETs = 104; Equivalent Gates = 26