LAN9218I-MT集成電路（IC）的控制器規(guī)格書PDF中文資料

General Description

The LAN9218I is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9218I has been specifically architected to provide the highest performance possible for any given architecture. The LAN9218I is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.

The LAN9218I includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit and 32-bit microprocessors and microcontrollers . The LAN9218I includes large transmit and receive data FIFOs with a high-speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN9218I memory buffer architecture allows the most efficient use of memory resources by optimizing packet granularity.

PRODUCT FEATURES

Highlights

■ Optimized for the highest performance applications

■ Efficient architecture with low CPU overhead

■ Easily interfaces to most 32-bit and 16-bit embedded CPU’s

■ Integrated PHY with HP Auto-MDIX

■ Supports audio & video streaming over Ethernet: multiple high-definition (HD) MPEG2 streams

■ Compatible with other members of LAN9218 family

Target Applications

■ Video distribution systems, multi-room PVR

■ Cable, satellite, and IP set-top boxes

■ Digital video recorders and DVD recorder/players

■ High definition televisions

■ Digital media clients/servers and home gateways

■ Video-over IP Solutions, IP PBX & video phones

■ Wireless routers & access points

■ High-end audio distribution systems

Key Benefits

■ Non-PCI Ethernet controller for the highest performance applications

— Highest performing non-PCI Ethernet controller

— 32-bit interface with fast bus cycle times

— Burst-mode read support

■ Eliminates dropped packets

— Internal buffer memory can store over 200 packets

— Automatic PAUSE and back-pressure flow control

■ Minimizes CPU overhead

— Supports Slave-DMA

— Interrupt Pin with Programmable Hold-off timer

■ Reduces system cost and increases design flexibility

■ SRAM-like interface easily interfaces to most embedded CPU’s or SoC’s

■ Reduced Power Modes

— Numerous power management modes

— Wake on LAN*

— Magic packet wakeup*

— Wakeup indicator event signal

— Link Status Change

■ Single chip Ethernet controller

— Fully compliant with IEEE 802.3/802.3u standards

— Integrated Ethernet MAC and PHY

— 10BASE-T and 100BASE-TX support

— Full- and Half-duplex support

— Full-duplex flow control

— Backpressure for half-duplex flow control

— Preamble generation and removal

— Automatic 32-bit CRC generation and checking

— Automatic payload padding and pad removal

— Loop-back modes

■ Flexible address filtering modes

— One 48-bit perfect address

— 64 hash-filtered multicast addresses

— Pass all multicast

— Promiscuous mode

— Inverse filtering

— Pass all incoming with status report

— Disable reception of broadcast packets

■ Integrated 10/100 Ethernet PHY

— Supports HP Auto-MDIX

— Auto-negotiation

— Supports energy-detect power down

■ High-Performance host bus interface

— Simple, SRAM-like interface

— 32 or 16-bit data bus

— 16Kbyte FIFO with flexible TX/RX allocation

— One configurable host interrupt

■ Miscellaneous features

— Low-profile, green, lead-free 100-pin TQFP package

— Integrated 1.8V regulator

— General Purpose Timer

— Optional EEPROM interface

— Support for 3 status LEDs multiplexed with Programmable GPIO signals

■ Single 3.3V Power Supply with 5V tolerant I/O

■ -40 to 85°C