LC4512V-10T176I集成電路（IC）的CPLD（復(fù)雜可編程邏輯器件）規(guī)格書PDF中文資料

ispMACH 4000 Introduction

The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend of Lattice’s two most popular architectures: the ispLSI? 2000 and ispMACH 4A. Retaining the best of both families, the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family.

Features

■ High Performance

? fMAX = 400MHz maximum operating frequency

? tPD = 2.5ns propagation delay

? Up to four global clock pins with programmable clock polarity control

? Up to 80 PTs per output

■ Ease of Design

? Enhanced macrocells with individual clock, reset, preset and clock enable controls

? Up to four global OE controls

? Individual local OE control per I/O pin

? Excellent First-Time-FitTM and refit

? Fast path, SpeedLockingTM Path, and wide-PT path

? Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders

■ Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)

? Typical static current 10μA (4032Z)

? Typical static current 1.3mA (4000C)

? 1.8V core low dynamic power

? ispMACH 4000Z operational down to 1.6V VCC

■ Broad Device Offering

? Multiple temperature range support

– Commercial: 0 to 90°C junction (Tj)

– Industrial: -40 to 105°C junction (Tj)

– Extended: -40 to 130°C junction (Tj)

? For AEC-Q100 compliant devices, refer to LA-ispMACH 4000V/Z Automotive Data Sheet

■ Easy System Integration

? Superior solution for power sensitive consumer applications

? Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

? Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies

? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces

? Hot-socketing

? Open-drain capability

? Input pull-up, pull-down or bus-keeper

? Programmable output slew rate

? 3.3V PCI compatible

? IEEE 1149.1 boundary scan testable

? 3.3V/2.5V/1.8V In-System Programmable (ISP?) using IEEE 1532 compliant interface

? I/O pins with fast setup path

? Lead-free package options