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LC4512V-75F256I中文資料萊迪思數(shù)據(jù)手冊PDF規(guī)格書

LC4512V-75F256I
廠商型號

LC4512V-75F256I

功能描述

3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

文件大小

483.61 Kbytes

頁面數(shù)量

74

生產(chǎn)廠商 Lattice Semiconductor
企業(yè)簡稱

Lattice萊迪思

中文名稱

萊迪思半導(dǎo)體公司官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-1-1 23:00:00

LC4512V-75F256I規(guī)格書詳情

ispMACH 4000 Introduction

The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend of Lattice’s two most popular architectures: the ispLSI? 2000 and ispMACH 4A. Retaining the best of both families, the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family.

Features

■ High Performance

? fMAX = 400MHz maximum operating frequency

? tPD = 2.5ns propagation delay

? Up to four global clock pins with programmable clock polarity control

? Up to 80 PTs per output

■ Ease of Design

? Enhanced macrocells with individual clock, reset, preset and clock enable controls

? Up to four global OE controls

? Individual local OE control per I/O pin

? Excellent First-Time-FitTM and refit

? Fast path, SpeedLockingTM Path, and wide-PT path

? Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders

■ Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)

? Typical static current 10μA (4032Z)

? Typical static current 1.3mA (4000C)

? 1.8V core low dynamic power

? ispMACH 4000Z operational down to 1.6V VCC

■ Broad Device Offering

? Multiple temperature range support

– Commercial: 0 to 90°C junction (Tj)

– Industrial: -40 to 105°C junction (Tj)

– Extended: -40 to 130°C junction (Tj)

? For AEC-Q100 compliant devices, refer to LA-ispMACH 4000V/Z Automotive Data Sheet

■ Easy System Integration

? Superior solution for power sensitive consumer applications

? Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

? Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies

? 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces

? Hot-socketing

? Open-drain capability

? Input pull-up, pull-down or bus-keeper

? Programmable output slew rate

? 3.3V PCI compatible

? IEEE 1149.1 boundary scan testable

? 3.3V/2.5V/1.8V In-System Programmable (ISP?) using IEEE 1532 compliant interface

? I/O pins with fast setup path

? Lead-free package options

產(chǎn)品屬性

  • 型號:

    LC4512V-75F256I

  • 功能描述:

    CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD

  • RoHS:

  • 制造商:

    Lattice

  • 存儲類型:

    EEPROM

  • 大電池數(shù)量:

    128

  • 最大工作頻率:

    333 MHz

  • 延遲時間:

    2.7 ns

  • 可編程輸入/輸出端數(shù)量:

    64

  • 工作電源電壓:

    3.3 V

  • 最大工作溫度:

    + 90 C

  • 最小工作溫度:

    0 C

  • 封裝/箱體:

    TQFP-100

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LATTICE/萊迪斯
24+
65200
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原裝現(xiàn)貨!實單直說!特價!
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23+
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12800
正規(guī)渠道,只有原裝!
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56000
公司進(jìn)口原裝現(xiàn)貨 批量特價支持
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