UPD78320GJ-5BJ中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

FEATURES

· Internal 16-bit architecture and external 8-bit data bus

· High-speed processing by pipeline control and instruction prefetch

? Minimum instruction execution time: 250 ns (with 16 MHz external clock in operation)

· Instruction set suitable for control operations (mPD78312 upward compatible)

? Multiplication/division instruction (16 bits ′ 16 bits, 32 bits ? 16 bits)

? Bit manipulation instruction

? String instruction, etc.

· On-chip high-function interrupt controller

? 3-level priority specifiable

? 3-type interrupt servicing mode selectable

(Vectored interrupt function, context switching function, and macro service function)

· Variety of peripheral hardware

? Realtime pulse unit

? 8-channel, 10-bit A/D converter

? Watchdog timer

· Powerful serial interface (with an on-chip dedicated baud rate generator)

? UART ····· 1 channel

? SBI (NEC Standard Serial Bus Interface)

? 3-wire serial I/O

····· 1 channel