LH28F008SAT-12中文資料夏普微數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The LH28F008SA is a high-performance 8M (8,388,608 bit) memory organized at 1M (1,048,576 bytes) of 8 bits each. Sixteen 64K (65,536 Byte) blocks are included on the LH28F008SA. A memory map is shown in Figure 4 of this specification. A block erase operation erases one of the sixteen blocks of memory in typically 1.6 seconds, independent of the remaining blocks. Each block can be independently erased and written 100,000 cyles. Erase Suspend mode allows sys tem software to suspend block erase to read data or execute code from any other block of the LH28F008SA.

FEATURES

? Very High-Performance Read

– 85 ns Maximum Access Time

? High-Density Symmetrically Blocked Architecture

– Sixteen 64K Blocks

? Extended Cycling Capability

– 100,000 Block Erase Cycles

– 1.6 Million Block Erase Cycles per Chip

? Automated Byte Write and Block Erase

– Command User Interface

– Status Register

? System Performance Enhancements

– RY?/BY? Status Output

– Erase Suspend Capability

? Deep-Powerdown Mode

– 0.20 μA ICC Typical

? SRAM-Compatible Write Interface

? Hardware Data Protection Feature

– Erase/Write Lockout during Power Transitions

? Independent Software Vendor Support

– Microsoft Flash File System? (FFS)

? ETOX? Nonvolatile Flash Technology

– 12 V Byte Write/Block Erase

? Industry Standard Packaging

– 40-Pin 1.2 mm × 10 mm × 20 mm TSOP (Type I) Package

– 44-Pin 600-mil SOP Package