LH28F800BJB-PTTL90中文資料夏普微數(shù)據(jù)手冊(cè)PDF規(guī)格書

8M-BIT ( 512Kbit ×16 / 1Mbit ×8 ) Boot Block Flash MEMORY

The product is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications.

The product can operate at VCC=2.7V-3.6V and VCCW=2.7V-3.6V or 11.7V-12.3V. Its low voltage operation capability realize battery life and suits for cellular phone application.

Its Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications.

■ Low Voltage Operation

― VCC=VCCW=2.7V-3.6V Single Voltage

■ OTP(One Time Program) Block

― 3963 word + 4 word Program only array

■ User-Configurable ×8 or ×16 Operation

■ High-Performance Read Access Time

― 90ns(VCC=2.7V-3.6V)

■ Operating Temperature

― 0°C to +70°C

■ Low Power Management

― Typ. 2μA (VCC=3.0V) Standby Current

― Automatic Power Savings Mode Decreases ICCR in Static Mode

― Typ. 120μA (VCC=3.0V, TA=+25°C, f=32kHz) Read Current

■ Optimized Array Blocking Architecture

― Two 4K-word (8K-byte) Boot Blocks

― Six 4K-word (8K-byte) Parameter Blocks

― Fifteen 32K-word (64K-byte) Main Blocks

― Top Boot Location

■ Extended Cycling Capability

― Minimum 100,000 Block Erase Cycles

■ Enhanced Automated Suspend Options

― Word/Byte Write Suspend to Read

― Block Erase Suspend to Word/Byte Write

― Block Erase Suspend to Read

■ Enhanced Data Protection Features

― Absolute Protection with VCCW≤VCCWLK

― Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Lockout during Power Transitions

― Block Locking with Command and WP#

― Permanent Locking

■ Automated Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration

― Command User Interface (CUI)

― Status Register (SR)

■ SRAM-Compatible Write Interface

■ Chip-Size Packaging

― 48-Ball CSP

■ ETOXTM* Nonvolatile Flash Technology

■ CMOS Process (P-type silicon substrate)

■ Not designed or rated as radiation hardened