LM3S617-IQN50-A0T中文資料etc未分類(lèi)制造商數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

[Luminary Micro, Inc.]

Architectural Overview

The Luminary Micro Stellaris? family of microcontrollers—the first ARM? Cortex?-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

The LM3S617 controller in the Stellaris family offers the advantages of ARM’s widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the controller uses ARM’s Thumb?-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost.

Luminary Micro offers a complete solution to get to market quickly, with a customer development board, white papers and application notes, and a strong support, sales, and distributor network.

Product Features

The LM3S617 microcontroller includes the following product features:

■ 32-Bit RISC Performance

– 32-bit ARM? Cortex?-M3 v7M architecture optimized for small-footprint embedded applications

– System timer (SysTick) provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism

– Thumb?-compatible Thumb-2-only instruction set processor core for high code density

– 50-MHz operation

– Hardware-division and single-cycle-multiplication

– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling

– 26 interrupts with eight priority levels

– Memory protection unit (MPU) provides a privileged mode for protected operating system functionality

– Unaligned data access, enabling data to be efficiently packed into memory

– Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control

■ Internal Memory

– 32-KB single-cycle flash

? User-managed flash block protection on a 2-KB block basis

? User-managed flash data programming

? User-defined and managed flash-protection block

– 8-KB single-cycle SRAM

■ General-Purpose Timers

– Three timers, each of which can be configured: as a single 32-bit timer, as two 16-bit timers, or to initiate an ADC event

– 32-bit Timer modes:

? Programmable one-shot timer

? Programmable periodic timer

? Real-Time Clock when using an external 32.768-KHz clock as the input

? User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug

? ADC event trigger

– 16-bit Timer modes:

? General-purpose timer function with an 8-bit prescaler

? Programmable one-shot timer

? Programmable periodic timer

? User-enabled stalling when the controller asserts CPU Halt flag during debug

? ADC event trigger

– 16-bit Input Capture modes:

? Input edge count capture

? Input edge time capture

– 16-bit PWM mode:

? Simple PWM mode with software-programmable output inversion of the PWM signal

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