LRS1331中文資料夏普微數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The LRS1331 is a combination memory organized as 1,048,576 × 16-bit flash memory and 262,144 × 16-bit static RAM in one package.

FEATURES

? Flash Memory and SRAM

? Stacked Die Chip Scale Package

? 72-ball 8 mm × 11 mm CSP plastic package

? Power supply: 2.7 V to 3.6 V

? Operating temperature: -25°C to +85°C

? Flash Memory

– Access time (MAX.): 90 ns

– Operating current (MAX.)

(The current for F-VCC pin and F-VCCW pin):

– Read: 25 mA (tCYCLE = 200 ns)

– Word write: 57 mA

– Block erase: 42 mA

– Standby current (the current for F-VCC pin): 15 μA

(MAX. F-RP ≤ GND ± 0.2 V)

– Optimized array blocking architecture

– Two 4K-word boot blocks

– Six 4K-word parameter blocks

– Thirty-one 32K-word main blocks

– Bottom boot location

– Extended cycling capability

– 100,000 block erase cycles

– Enhanced automated suspend options

– Word write suspend to read

– Block erase suspend to word write

– Block erase suspend to read

? SRAM

– Access time (MAX.): 85 ns

– Operating current: 45 mA (MAX.)

– Standby current: 15 μA (MAX.)

– Data retention current: 2 μA (MAX.)