M1040-11-155.5200中文資料ICST數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

GENERALDESCRIPTION

The M1040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in OC-12/48 class optical networking systems. It features dual differential inputs with two modes of input selection: manual and

automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. This device provides two outputs. External loop components allow the tailoring of PLL loop response.

FEATURES

◆Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz)

◆Output frequencies of 62.5 to 175 MHz; Two differen tial LVPECL outputs (CML, LVDS options available)

◆Loss of Lock (LOL) indicator output

◆Narrow Bandwidth control input (NBW pin); Initialization (INIT) input overrides NBW at power-up

◆Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL

◆AutoSwitch (AUTOpin) - automatic (non-revertive) reference clock reselection upon clock failure; Hitless Switching (HS), Phase Build-out (PBO) options enable SONET (GR-253)/SDH (G.813)MTIE/TDEV compliance

◆Acknowledge pin (REF_ACKpin) indicates the actively selected reference input

◆Industrial temperature available

◆Single 3.3V power supply

◆Small 9 x 9 mm SMT (surface mount) package