M2004-01-622.0800集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

DESCRIPTION

The M2004-01 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Translator in a 9mm x 9mm surface mount package.

The internal high “Q” SAW filter provides low jitter signal performance and determines the maximum output frequency of the VCSO. A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz.

The input to the Frequency Translator is provided by selecting between one of two output reference clocks. The output frequency is an integer multiple of the input reference frequency.

Parallel and serial control of the output and feedback dividers is provided via the configuration logic. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock.

The M2004-01 is available at SONET/SDH and 10GbE frequencies up to 700MHz.

FEATURES

■ Output Clock Frequency up to 700MHz

■ Differential LVPECL Outputs

■ Internal Low-jitter SAW-based Oscillator

■ Intrinsic Jitter <1ps rms (12kHz - 20MHz)

■ Jitter Attenuation of Input Reference Clock

■ Dual Input MUX

■ Parallel Programming

■ Tunable Loop Filter Response

■ Differential LVPECL Outputs

■ 3.3V Operation

■ Small 9mm x 9mm SMT Package

APPLICATIONS

■ SONET / SDH / 10GbE System Synchronization

■ Add / Drop Muxes, Access and Edge Switches

■ Line Card System Clock Cleaner / Translator

■ Optical Module Clock Cleaner / Translator