M28C64-25KA3T中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The M28C64 devices consist of 8192x8 bits of low power, parallel EEPROM, fabricated with STMicroelectronics’ proprietary single polysilicon CMOS technology. The devices offer fast access time, with low power dissipation, and require a single voltage supply (5V or 3V, depending on the option chosen).

The device has been designed to offer a flexible microcontroller interface, featuring both hardware and software handshaking, with Ready/Busy, Data Polling and Toggle Bit. The device supports a 64 byte Page Write operation. Software Data Protection (SDP) is also supported, using the standard JEDEC algorithm.

■ Fast Access Time:

– 90 ns at VCC=5 V forM28C64 and M28C64-A

– 120 ns at VCC=3 V for M28C64-xxW

■ Single Supply Voltage:

– 4.5 V to 5.5 V for M28C64 and M28C64-A

– 2.7 V to 3.6 V for M28C64-xxW

■ Low Power Consumption

■ Fast BYTE and PAGE WRITE (up to 64 Bytes)

– 1 ms at VCC=4.5 V for M28C64-A

– 3 ms at VCC=4.5 V for M28C64

– 5 ms at VCC=2.7 V for M28C64-xxW

■ Enhanced Write Detection and Monitoring:

– Ready/Busy Open Drain Output

– Data Polling

– Toggle Bit

– Page Load Timer Status

■ JEDEC Approved Bytewide Pin-Out

■ Software Data Protection

■ 100000 Erase/Write Cycles (minimum)

■ Data Retention (minimum):

– 40 Years for M28C64 and M28C64-xxW

– 10 Years for M28C64-A