M2V28S20TP-6中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.

M2V28S20TP,M2V28S30TP,M2V28S40TP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.

FEATURES

- Single 3.3V ±0.3V power supply

- Max. Clock frequency -6:PC133 / -7:PC100 / -8:PC100

- PC133(-6) supports x4/x8 only. And does not support Low-Power (L) version.

- Fully synchronous operation referenced to clock rising edge

- 4-bank operation controlled by BA0,BA1(Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/FP (programmable)

- Burst type- Sequential and interleave burst (programmable)

- Byte Control- DQML and DQMU (M2V28S40TP)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- Auto and self refresh

- 4096 refresh cycles /64ms

- LVTTL Interface

- Package

M2V28S20TP/30TP/40TP

400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch