M2V56S30中文資料三菱電機數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit,

M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit,

M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit,

synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of

CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),

and are suitable for main memory or graphic memory in computer systems.

- Single 3.3v + 0.3V power supply

- Max. Clock frequency -5:PC133 / -6:PC133 / -7:PC100

- Fully Synchronous operation referenced to clock rising edge

- Single Data Rate

- 4 bank operation controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/full page (programmable)

- Burst type- sequential / interleave (programmable)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- 8192 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

- LVTTL Interface

- Both 54-pin TSOP Package and 64-pin Small TSOP Package

M2V56S*0ATP: 0.8mm lead pitch 54-pin TSOP Package

M2V56S*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package (sTSOP)

- Low Power for the Self Refresh Current ICC6 : 2.0mA (–5L,-6L,-7L)

- Ultra Low Power for the Self Refresh Current ICC6 : 1.0mA (–5UL,-6UL,-7UL)