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M2V64S3DTP-6中文資料三菱電機(jī)數(shù)據(jù)手冊PDF規(guī)格書
M2V64S3DTP-6規(guī)格書詳情
DESCRIPTION
M2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2V64S20DTP, M2V64S30DTP and M2V64S40DTP achieve very high speed data rate up to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency -6:133MHz, -7:100MHz, -8:100MHz
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst type- sequential and interleave (programmable)
- Byte Control- DQML and DQMU for M2V64S40DTP
- Random column access
- Auto precharge and All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles every 64ms
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
產(chǎn)品屬性
- 型號：
M2V64S3DTP-6
- 制造商：
MITSUBISHI
- 制造商全稱：
Mitsubishi Electric Semiconductor
- 功能描述：
64M Synchronous DRAM
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
MIT |
23+ |
NA/ |
980 |
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價(jià) | ||
MITSUBIS |
2016+ |
TSSOP54 |
3000 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價(jià) | ||
MITSUBIS |
22+ |
TSSOP |
3000 |
原裝正品,支持實(shí)單 |
詢價(jià) | ||
MITSUBIS |
TSSOP54 |
1200 |
正品原裝--自家現(xiàn)貨-實(shí)單可談 |
詢價(jià) | |||
MIT |
2402+ |
TSOP |
8324 |
原裝正品!實(shí)單價(jià)優(yōu)! |
詢價(jià) | ||
MITSUBIS |
22+ |
TSOP |
2000 |
原裝正品現(xiàn)貨 |
詢價(jià) | ||
MIT |
24+ |
TSOP |
30 |
詢價(jià) | |||
MIT |
2020+ |
TSOP54 |
4500 |
百分百原裝正品 真實(shí)公司現(xiàn)貨庫存 本公司只做原裝 可 |
詢價(jià) | ||
MIT |
TSOP |
30 |
原裝現(xiàn)貨海量庫存歡迎咨詢 |
詢價(jià) | |||
MIT |
21+ |
TSSOP-54 |
5000 |
原裝現(xiàn)貨/假一賠十/支持第三方檢驗(yàn) |
詢價(jià) |
