M36W0R6050T1ZAQE中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The M36W0R6050T1 and M36W0R6050B1 combine two memories in a Multi-Chip Package:

● a 64-Mbit, Multiple Bank Flash memory, the M58WR064HT/B, and

● a 32-Mbit Pseudo SRAM, the M69KB048BD.

The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58WR064HT/B and M69KB048BD datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from the ST web site: www.st.com.

Features

■ Multi-Chip Package

– 1 die of 64 Mbit (4 Mb × 16) Flash memory

– 1 die of 32 Mbit (2 Mb × 16) Pseudo SRAM

■ Supply voltage

– VDDF = VDDP = VDDQF = 1.7 V to 1.95 V

■ Low power consumption

■ Electronic signature

– Manufacturer Code: 20h

– Device code (top flash configuration), M36W0R6050T1: 8810h

– Device code (bottom flash configuration), M36W0R6050B1: 8811h

■ Package

– ECOPACK?

Flash memory

■ Programming time

– 8 μs by Word typical for Fast Factory Program

– Double/Quadruple Word Program option

– Enhanced Factory Program options

■ Memory blocks

– Multiple Bank memory array: 4 Mbit Banks

– Parameter Blocks (Top or Bottom location)

■ Synchronous / Asynchronous Read

– Synchronous Burst Read mode: 66 MHz

– Asynchronous/ Synchronous Page Read mode

– Random Access: 70 ns

■ Dual operations

– Program Erase in one Bank while Read in others

– No delay between Read and Write operations

■ Block locking

– All blocks locked at Power-up

– Any combination of blocks can be locked

– WPF for Block Lock-Down

■ Security

– 128-bit user programmable OTP cells

– 64-bit unique device number

■ Common Flash Interface (CFI)

■ 100 000 program/erase cycles per block

PSRAM

■ Access time: 70 ns

■ Asynchronous Page Read

– Page size: 8 words

– First access within page: 70 ns

– Subsequent read within page: 20 ns

■ Three Power-down modes

– Deep Power-Down

– Partial Array Refresh of 4 Mbits

– Partial Array Refresh of 8 Mbits