M48Z128集成電路（IC）的存儲(chǔ)器規(guī)格書PDF中文資料

M48Z128屬于集成電路（IC）的存儲(chǔ)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的M48Z128存儲(chǔ)器存儲(chǔ)器是集成電路上用作數(shù)據(jù)存儲(chǔ)設(shè)備的半導(dǎo)體器件。這些器件分為非易失性或易失性兩種，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲(chǔ)容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線、SPI、UFS、Xccela 總線和 1-線。

Description

The M48Z128/Y/V ZEROPOWER? RAM is a 128 Kbit x 8 non-volatile static RAM organized as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP module to provide a highly integrated batterybacked memory solution.

Features

■ Integrated, ultra low power SRAM, power-fail

control circuit, and battery

■ Conventional SRAM operation; unlimited

WRITE cycles

■ 10 years of data retention in the absence of

power

■ Battery internally isolated until power is first

applied

■ Automatic power-fail chip deselect and WRITE

protection

■ WRITE protect voltages:

(VPFD = power-fail deselect voltage)

– M48Z128: VCC = 4.75 to 5.5 V

4.5 V ≤ VPFD ≤ 4.75 V

– M48Z128Y: VCC = 4.5 to 5.5 V

4.2 V ≤ VPFD ≤ 4.5 V

– M48Z128V: VCC = 3.0 to 3.6 V

2.8 V ≤ VPFD ≤ 3.0 V

(contact ST sales office for availability)

■ Pin and function compatible with JEDEC

standard 128 K x 8 SRAMs

■ RoHS compliant

– Lead-free second level interconnect